Electronic circuits, such as integrated circuits or chips, are used in most products that have electronic components. A typical integrated circuit (IC) design is initially conceived by a circuit designer, with a number of components and devices connected to generate a circuit with desired performance and characteristics. Once the circuit designer has designed an electronic circuit, the circuit is reconfigured from the schematic format into a geometric layout format specifying a suitable semiconductor implementation of the circuit.
A large number of components in the IC may be facilitated with an electronic design automation (EDA) tool that allows a circuit designer to position and connect various shapes on the IC. The circuit designer can create a custom design of such ICs, printed-circuit boards, and other electronic circuits containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated using EDA technologies that typically run on an operating system in conjunction with a processor-based computer system.
Circuit designers may use different methods to verify the functionality and power consumption of the generated electronic circuit designs. One common method of verifying is to simulate the designed electronic circuit. Simulating a circuit design dynamically verifies the circuit design by monitoring behaviors of the design, often under controlled parameters. For many types of circuit designs, simulation can be performed during the design process to ensure that the ultimate functionality will be achieved by the fabricated circuit. Therefore, an exploding demand for high performance electronic products has increased the interest in efficient and accurate simulation techniques for integrated circuits. For analog designs, an analog-based simulation approach is commonly used to implement simulation of the design, and for digital circuits, equivalent digital simulation is performed.
The primary goal of the computer-aided design simulations is to verify the electrical characteristics of a circuit design. The electrical characteristics of a circuit design may be significantly impacted by physical dimensions such as, gate oxide thickness, gate width, length, shape of the poly gate at the bottom, and spacer width. Current semiconductor fabrication techniques have advanced to create fairly simple geometrical shapes for these dimensional features. As a result, simple geometrical rules may be sufficient for these critical dimensions within the circuit design. However, as circuit design dimensions continue to shrink, semiconductor fabrication processes or techniques require more complex techniques to meet the design goals. Because of this shrinking in the circuit design dimensions and increase in the circuit design complexities, the electric properties of wires have become more prominent, and chips are more susceptive to breakdown due to, for example, antenna effect or to wear out over time due to, for example, electromigration (EM). Accordingly, in order to ensure the proper operation of the circuit design, there are many types of electrical analyses that are needed to be performed to check for potential problems relating to EM effects and voltage (IR) drops.
As the modern day circuit designs comprise several millions of instances of circuit devices, current computer-aided simulation and analysis techniques being employed on the circuit designs to check for potential problems relating to IR drops and EM effect use a lot of computing power and have a large runtime. For example, a conventional computer-aided flat simulation technique employed on a large size circuit design considers the circuit design as a flat design with no top level and block level boundaries. Such flat simulation method merges both top level and block level netlists, and then the merged top level and block level netlists are simulated together as one single netlist. In this flat simulation technique, operational performance and capacity becomes a huge bottleneck as the circuit design increase in size and complexity due to simulating the combined top level and block level netlists. Also, the flat simulation method doesn't provide any technique to view and analyze EM and IR values determined for the block level and the top level separately, and thereby imposing a challenge when a circuit designer wants to debug and fix the EM and IR issues for the block level and the top level of the circuit design individually.
In another example, a conventional computer-aided simulation technique employed on a large size electronic circuit design initially employs a block level macro modeling to create a single resistance and capacitance (RC) model for a full block, and then attach a full block current to a single pin. Such block models are then used in a top level simulation run as black box. This black box modeling of the blocks of the circuit design in simulation of the top design of the circuit design does not provide accurate power-grid EM and IR results as that requires distributed current model across a power-grid network inside the block level of the circuit design. Also, this simulation method doesn't provide any technique to view and analyze the EM and IR values determined for the block level, and thereby imposing a challenge when a circuit designer wants to debug and fix the EM and IR issues of the circuit design.
Therefore, there is a need for methods and systems that addresses the above mentioned drawbacks of the conventional techniques employed for simulation of increasingly large and complex circuit designs to achieve high performance with comparative accuracy while simulating large size circuit designs, and thereby allowing the EM and IR sign-off for large and complex electronic circuit designs.